1. Field of the Invention
The present invention relates to an image processing apparatus and camera system applicable to a digital camera and the like, and more particularly to management technologies for a video memory.
2. Description of Related Art
FIG. 1 is a block diagram showing an example of the structure of a video signal processing apparatus incorporating typical video memory management technologies and being applicable to a digital camera and the like.
The image processing apparatus 100 shown in FIG. 1 has: a plurality of video processors 101-1 to 101-m (in the example shown in FIG. 1, m=4); a video memory (also called a temporary video memory in some cases) 102 used as a shared memory for temporarily recording images; a video bus 103 used for accessing the video memory 102; a plurality of ports 104-1 to 104-4 for data processing such as compression and calculation and for data conversion for accessing the video bus 103; a central processing unit (CPU) 105 for performing various settings to each port 104-1 to 104-4 such as arrangement and attribute information on video data, control information and the like; a local bus 106 for data transfer between CPU 105 and each port 104-1 to 104-4; and image processing data buses 107-1 to 107-4 for transferring image processing data from each video processor 101-1 to 101-4 to a corresponding one of the ports 104-1 to 104-4.
Each port 104-1 to 104-4 has a read port and a write port.
In the structure of the image processing apparatus 100, CPU 105 sets arrangement information on video data in the video memory 102 and a control signal to each port 104-1 to 104-4 to transfer data between each video processor 101-1 to 101-4 connected to each port 104-1 to 104-4 and the temporary video memory 102 connected to the video bus 103.
FIG. 2 is a flow chart showing the outline of a read/write process of the image processing apparatus 100 shown in FIG. 1.
In the image processing apparatus 100, CPU 105 sets arrangement and attribute information on video data in the temporary video memory 102 and control information to each port 104-1 to 104-4. Each video processor 101-1 to 101-4 sends a data control signal to the ports 104-1 to 104-4 to perform data transfer between each video processor and the temporary video memory 102.
If the arrangement and attribute information on video data in the temporary video memory 102 or the control information for each port 104-1 to 104-4 is required to be changed, each video processor 101-1 to 101-4 issues an interrupt to CPU 105, and after an address and a control signal set to each port 104-1 to 104-4 are changed, a data control signal is transferred to each port 104-1 to 104-4.
Then, as shown in FIG. 2, CPU 105 judges whether a port is a read port or not (ST1), and if it is judged that the port is the read port, a read address of the video memory 102 is set to the read port of the port 104 (-1 to -4) via the local bus 106 (ST2).
Next, the read port executes a read transaction via the video bus 103 (ST3).
Data read from the video memory 102 by the read transaction is received at the read port (ST4).
Next, the read data received at the read port is output to the video processor 101 (-1 to -4) (ST5).
If CPU 105 judges at Step ST1 that the port is not the read port but the write port, a write address of the video memory 102 is set to the write port of the port 104 (-1 to -4) via the local bus 106 (ST6).
The corresponding video processor 101 (-1 to -4) outputs data to be written in the video memory 102 to the write port (ST7).
The write port executes a write transaction via the video bus 103 to write data received from the video processor 101 (-1 to -4) in the video memory 102 (ST8).
A variety of memory management technologies for an image processing apparatus have been proposed (e.g., refer to Japanese Patent Application Publications No. HEI-7-93210, Patent Document 1, and No. 2003-316646, Patent Document 2).
Patent Document 1 discloses a shared memory management scheme in which in response to a request from a plurality of processes, a page table converts a physical address into a logical address to improve a memory usage efficiency.
Japanese Patent Unexamined Publication No. 2003-316646 discloses a memory management scheme in which a virtual memory is managed on a page unit basis for a plurality of processes to improve a memory usage efficiency.